The HEMT is a type of field effect transistor (FET) having a heterojunction between a channel layer and a barrier layer whose electron affinity is smaller than that of the channel layer. A group III-V HEMT device is one made of materials in column III of the periodic table, such as aluminum (Al), gallium (Ga), and indium (In), and materials in column V of the periodic table, such as nitrogen (N), phosphorus (P), and arsenic (As). A two-dimensional electron gas (2DEG) forms in the channel layer of a group III-V HEMT device due to the mismatch in polarization field at the channel-barrier layer interface. The 2DEG has a high electron mobility that facilitates high-speed switching during device operation.
In typical HEMT devices, the 2DEG arises naturally at the interface of the III-V materials forming the heterojunction, meaning the typical HEMT device will conduct current in the absence of a gate potential. In other words, the typical HEMT device is a normally “on” device. A negatively-biased voltage may be applied to the gate electrode to deplete the 2DEG and thereby turn off the device. Accordingly, the typical HEMT device is also referred to as a “depletion-mode” HEMT. However, the typical depletion-mode HEMT device's normally on state makes it unsuitable for many applications as the depletion-mode HEMT device conducts current before other circuitry is fully powered and operational.
To resolve this issue, a number of different approaches have been explored to create a normally “off”, or “enhancement-mode” HEMT device. One of these approaches is to form a P-N junction gate to deplete the 2DEG by raising the potential of the current conducting 2DEG channel and therefore deplete the carriers from the channel at zero gate bias. FIG. 1 shows a cross-sectional view of a prior art structure for a P-N junction gate HEMT device. The HEMT device 100 shown in FIG. 1 comprises a substrate 102, a channel layer 104, and a barrier layer 106 formed in a stacked structure, with the heterojunction between the channel layer 104 and barrier layer 106 giving rise to a current carrying 2DEG channel. A gate layer 108 is formed on the barrier layer 106. The gate layer 108 is a P-type semiconductor material to raise the potential of the current carrying 2DEG channel. Electrodes 112 and 114 are formed on the barrier layer 108 to act as the source and drain, respectively, of the HEMT device 100. A gate electrode 110 is formed on the gate layer 108. During device operation of the foregoing HEMT device 100, a forward bias voltage relative to the substrate 102 is applied to the gate electrode 110 allowing a current to flow between the source electrode 112 and the drain electrode 114.
FIGS. 2A-2F shows cross-sectional views of the manufacturing steps for making the P-N junction gate HEMT device 100 of FIG. 1. In FIG. 2A, a gate layer 208 comprising a P-type semiconductor material is formed on a barrier layer 206, which in turn is formed on a channel layer 204 in a stacked structure on top of a substrate 202. A first mask layer 209 is deposited on the gate layer 208 for patterning of the gate layer 208. In FIG. 2B, exposed portions of the gate layer 208 that were not covered by the first mask layer 209 are etched away using a dry-etch process. The dry-etch process also removes the first mask layer 209.
In FIG. 2C, a second mask layer 211 is deposited over the gate layer 208 and the barrier layer 206 for patterning of the source and drain electrodes (shown in the next figure, FIG. 2G). A first metal layer 213 is deposited over the second mask layer 211 and the exposed portions of the barrier layer 206 not covered by the second mask layer 211. In FIG. 2D, a lift-off process is used to remove the second mask layer 211, taking along portions of the first metal layer 213 deposited on the second mask layer 211 and leaving only the portions of the first metal layer 213 deposited on the barrier layer 206, forming a source electrode 212 and a drain electrode 214. The source and drain electrodes 212 and 214 are then annealed at high temperature in a nitrogen (N2) rich environment to form an ohmic contact with the barrier layer 206.
In FIG. 2E, a third mask layer 215 is deposited over the source and drain electrodes 212 and 214, the barrier layer 206, and a portion of the gate layer 208 for patterning of the gate electrode (shown in the next figure, FIG. 2F). A second metal layer 217 is deposited over the third mask layer 215 and the exposed portion of the gate layer 208. In FIG. 2F, a lift-off process is once again used to remove the third mask layer 215 and portions of the second metal layer 217, leaving only the portions of the second metal layer 217 deposited on the gate layer 208, forming a gate electrode 210. Typically, the gate electrode 210 for conventional P-N junction gate HEMT devices comprises a metal material, such as nickel gold (NiAu). Forming an ohmic contact between the metal gate electrode 210 and the P-type semiconductor gate layer 208 requires annealing the metal gate electrode 210 in a mixed oxygen (O2) and nitrogen (N2). However, the presence of oxygen (O2) during the annealing of the gate electrode 210 will degrade the contact of the source and the drain electrodes 212 and 214, reducing the amount of current conducting from the source electrode 212 to the drain electrode 214.
In addition to degrading the source and drain electrode 212 and 214, there are a number of other issues with manufacturing a conventional P-N junction gate HEMT device 200 as shown in connection with FIGS. 2A-2F. To begin with, the alignment of the gate electrode 210 is difficult to control due to process variations during the patterning steps. Ideally, the gate electrode 210 will be centered on the gate layer 208. However, due to the realities of the manufacturing environment and because two patterning steps must be performed—one for the gate layer 208 and one for the gate electrode 210, deviations in the placement of the underlying gate layer 208 and the placement of the gate electrode 210 will frequently occur. This requires the length of the gate layer 208 to be much longer than the length of the gate electrode 210 to minimize the occurrence of the gate electrode 210 being placed off of the gate layer 208. In extreme cases, the gate electrode 210 may be offset such that it is formed off of the gate layer 208 and directly on the barrier layer 206, resulting in the shorting of the HEMT device and causing the HEMT device to be non-functional. To protect against shorting, if the gate electrode 210 is 2 μm in length, for example, than the gate layer 208 should be 3 μm-4 μm in length to account for misalignment between the gate electrode 210 and the gate layer 208 during manufacturing.
A longer gate layer 208 means the overall HEMT device must be larger, reducing the transistor density for a given semiconductor die area. Considering that most modern integrated circuits typically utilize hundreds of thousands to millions of transistors, high transistor density is highly desirable to maximize the number of integrated circuit dies formed on a single wafer to reduce manufacturing cost and for use in smaller end applications, such as mobile computing devices.
There is, therefore, an unmet demand for P-N junction gate HEMT devices having improved gate electrode alignment, improved conductivity, and allowing for a higher transistor density for a given semiconductor die area.